1. Field of the Invention
This invention relates to the field of MOS and bipolar (including Bi-MOS and Bi-CMOS) integrated circuits and more specifically to a process for making contact between transistor diffusion regions and between transistor diffusion regions and gate layer polysilicon on a silicon substrate. This contact method is coupled with the use of elevated source/drain type structures and silicidized or refractory metal local interconnect segments to form integrated circuits having an increased device density.
2. Prior Art
In the manufacture of semiconductor devices, there is a need to make electrical contacts between certain regions of the substrate. Prior art techniques have traditionally used the first and second metal layers or buried contacts to make contact between these regions. Prior art techniques first form device regions. The device regions may be transistors or may be small numbers of transistors connected together. The semiconductor surface is then covered by at least one layer of dielectric material. This dielectric is then masked and etched to form openings in the dielectric known as contact holes or vias. These openings expose the portions of the substrate which are to be contacted. Next, a layer of conductive material is deposited on the surface of the substrate so as to cover any overlying dielectric and to fill the openings. This layer is known as "first metal". The conductive material is then covered with photoresist. The photoresist is then patterned and an etch is performed to remove predetermined portions of the metal layer. The remaining photoresist is then removed leaving conductive material which has been patterned to form interconnect lines between the via openings. These interconnect lines electrically connect different device areas on the substrate and allow for electrical contact to external leads. Due to the requirements for increased density of semiconductor devices, the semiconductor manufacturing industry has increased the number of devices and features on any given semiconductor surface. Until recently, this process has consisted mainly of miniaturization of existing designs and components.
The first and second metalization layers seriously limit the density of integrated circuits. In prior art processes, the metal layers are used to connect the transistor drains of every CMOS inverter or gate and to connect the transistor drains to the gates of the next stage.
One method for forming a direct contact between p-channel and n-channel transistors and between diffusion and gate without the use of first metal is the use of self-aligned silicides. These self-aligned silicides are formed by depositing and annealing a layer of refractory metal. The refractory metal will react with the silicon to form a silicide and will react with the annealing gas to form a top refractory metal compound layer (often a nitride such as titanium nitride). Prior art methods traditionally have removed the refractory metal compound layer leaving the silicide as the conductive layer. One prior art process has formed local interconnects by using portions of the refractory metal compound layer formed by means of an additional photolithographic step as local interconnect pads (also called straps). One such process anneals titanium in a nitrogen environment to form titanium nitride and titanium silicide. The titanium nitride is then masked and selectively etched to form titanium nitride pads which form local interconnects over regions where silicide has not been formed. This titanium interconnect technology allows for minimum geometry junctions giving improved circuit performance and increased device density. This technology allows for local interconnects to be formed to connect transistor sources and drains of every inverter or gate and to connect the transistor drains with the gates of the next stage. But the prior art process of connecting gates using titanium silicide and/or titanium nitride interconnects does not provide for crossover of gates within a device region without contact to the crossover gates. Thus, prior art processes having non-electrically coupled crossover structures which pass through a device region still require the use of first metal. A crossing can be isolated by the use of a second polysilicon layer, but this layer presents serious step coverage problems as well as requiring additional undesired high temperature steps. Another drawback of the prior art contact processes is that they require dedicated diffusion areas resulting in significant contribution to junction capacitance and consequently slower circuit performance. What is needed is a method for forming local interconnects without the use of first metal which also allows for non-coupled crossover of gate structures and preferably reduced junction area.
Another problem with prior art processes is that the distance between N.sup.+ and P.sup.+ diffusion into single crystal silicon has to be maintained. If the distance between N.sup.+ and P.sup.+ diffusion areas is not maintained, latch-up will occur. What is needed is a process which will allow the source and drain structures to be placed closer together without causing latch-up.